Technical Field
Embodiments of the present disclosure related to stacked semiconductor packages and methods of forming same.
Description of the Related Art
Ongoing demand for smaller electronic devices pressures manufacturers of such devices to increase component density and reduce component size wherever possible within the device. Semiconductor fabricators have responded by increasing the use of chip scale packaging and wafer level packaging techniques to minimize the footprint of the semiconductor package, at times reducing the package to a size approaching the size of the semiconductor die itself. In particular, the use of direct surface mountable ball grid arrays and flip chip configurations has been implemented, thereby reducing semiconductor package sizes.
Space on a printed circuit board (PCB) has been conserved by vertically stack packages to form a stacked package, also referred to as a Package-on-Package (PoP) package. Stacked packages are packages that are stacked vertically and include one or more top packages vertically stacked over a bottom package. Stacked packages are typically more rigid that individual packages and in some case may cause warpage due to the rigidity and differing coefficients of thermal expansion of the varying materials within the stacked package. The rigidity of the stacked packages can result in decreased solder reliability when the package is coupled to the PCB.